The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high density semiconductor devices with submicron design features and active islands isolated by shallow insulated trenches.
Current demands for high density and performance associated with ultra large scale integration (ULSD require submicron features of significantly less than 0.25 microns, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions or islands, called active regions, active islands or, simply, islands, in which individual circuit components are formed. The electrical isolation of these active islands is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active islands. This type of isolation has been referred to as local oxidation of silicon, or LOCOS.
In an effort to enable the further reduction of the size of semiconductor devices, semiconductor-on-insulator (SOI) wafers increasingly have been used in very-large scale integration (VLSI) or ULSI of semiconductor devices. An SOI wafer typically has a thin layer of silicon on top of a layer of an insulator material. In SOI technology, the semiconductor device is formed entirely in and on the thin layer of silicon, and is isolated from the lower portion of the wafer by the layer of insulator material. In an SOI integrated circuit, essentially complete device isolation may be achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. One advantage which SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer. LOCOS isolation generally is not useful for SOI integrated circuits in VLSI and ULSI semiconductor devices, since it requires too large an area of silicon for oxidation.
Another type of isolation structure is known as trench isolation, wherein shallow isolation trenches are etched in the substrate between the sites of semiconductor devices and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. STI has been widely applied to VLSI and ULSI semiconductor devices, and has been applied recently to SOI integrated circuits for such devices.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate. A nitride layer may be deposited over the pad oxide. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer, if present, are then etched away, followed by etching away of the exposed pad oxide layer. Further etching continues into the thus-exposed substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the remaining nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality and to remove etching-induced damage. The trench is then refilled, such as by coating the entire surface of the semiconductor wafer with an insulating material (or xe2x80x9ctrench fillxe2x80x9d) such as an oxide, for example, silicon dioxide derived from tetraethyl orthosilicate (TEOS). When a nitride layer is present, the surface may then be planarized, as by chemical-mechanical polishing (CMP) using the nitride layer as a polish stop. In subsequent operations, the nitride and pad oxide are stripped off, and a gate oxide layer is grown on the exposed silicon of the substrate. When no nitride layer is present, the oxide coating is etched back by isotropic etching or polishing, so that the oxide layer remains in the trench. Thereafter, the wafer is further processed to form a semiconductor device.
Shallow trench isolation has several limitations, which may be exacerbated in SOI devices. One problem is that sharp corners at the top of the trench can result in junction leakage currents. More specifically, such sharp corners may cause unwanted increases in the sub-threshold currents in the channel regions along the edge of the device areas when the FETs are switched on. The device threshold voltage can also be lowered. In order to avoid these problems, it has been found desirable to round the corners of such trenches to increase the radius of curvature and thereby decrease the electric field at the corners. This has been accomplished by, for example, oxidizing the entire inner surface of the newly formed trench, taking advantage of the fact that an exposed corner of a silicon layer etches faster than a flat surface of the silicon layer, thus forming a rounded upper corner at the top of the trench.
However, with SOI devices, the corner rounding solution leads to a new problem. The new problem in SOI devices arises as a result of the proximity of the dielectric insulation layer below the silicon active layer. In SOI devices, the shallow isolation trench is etched through the silicon layer to the insulation layer. When the exposed portion of the silicon on the sidewalls of the newly formed trench is oxidized during the process of rounding the corners, a wedge or xe2x80x9cbird""s beakxe2x80x9d of new oxide may form on the underside of the silicon active layer adjacent the isolation trench, between the silicon active layer and the underlying layer of insulating material of the SOI wafer. Thus, as the oxide grows on the sidewalls of the trench, it may grow laterally between the lower edge of the silicon active layer and the underlying oxide insulation layer. In essence, during the process of oxidation which is intended to round the upper corner of the silicon active layer, the lower corner of the silicon active layer is also rounded, forming the bird""s beak or oxide wedge between the silicon active layer and the underlying oxide insulation layer. The problem becomes manifest when, during subsequent high temperature processing steps, thermal expansion of the bird""s beak creates strain-induced defects in the silicon crystal structure and/or lifts the silicon layer, due to the stress of the differently expanding oxide. The strain-induced defects in the crystal structure may change the electrical characteristics of the semiconductor. The lifting of the silicon layer distorts the surface of the semiconductor device from its desired planarity to an undesirable non-planar condition. As semiconductor device dimensions continue to become smaller, problems such as these both occur more easily and become less tolerable.
Thus, there exists a need for STI methodology applicable to SOI semiconductor devices wherein the problems resulting from sharp corners can be alleviated without creating the problems resulting from the bird""s beak on the underside of the silicon active layer adjacent the isolation trench.
The present invention provides a method of avoiding formation of the xe2x80x9cbird""s beakxe2x80x9d while providing rounded upper corners on the silicon active layer in shallow trench isolation of SOI semiconductor devices.
In one embodiment, the present invention relates to a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:
providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;
forming an isolation trench through the silicon active layer, the isolation trench defining at least one active island in the silicon active layer;
depositing a passivating insulator in a lower portion of the isolation trench; and
filling the isolation trench above the passivating insulator with a trench isolation material.
In one embodiment, the method further includes a step of rounding at least one corner of the active island in an upper portion of the silicon active layer.
In one embodiment, the step of depositing includes a directional deposition, whereby the passivating insulator is deposited substantially only in the lower portion of the isolation trench. In one embodiment, the directional deposition is by one of physical vapor deposition, sputtering, thermal CVD or a plasma enhanced method. In one embodiment, the step of depositing is followed by a step of etching away passivating insulator deposited on sidewalls of the isolation trench. In one embodiment, the step of depositing is followed by a step of selectively etching away passivating insulator deposited on sidewalls of the isolation trench.
In one embodiment, the method further comprises forming a liner in the isolation trench prior to filling the isolation trench.
In one embodiment, the passivating insulator comprises at least one of an oxide of silicon and a nitride of silicon.
In one embodiment, the insulation material is a dielectric. In one embodiment, the step of filling fills the isolation trench at least to a level substantially flush with an upper surface of the silicon active layer.
In another embodiment, the present invention relates to a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:
providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;
etching through the silicon active layer to form an isolation trench through the silicon active layer, the isolation trench defining at least one active island in the silicon active layer;
depositing a passivating insulator substantially only at the lower portion of the isolation trench;
rounding at least one corner of the active island in an upper portion of the silicon active layer;
forming a liner in the isolation trench; and
filling the isolation trench above the passivating insulator with a trench isolation material.
In one embodiment, the step of filling fills the isolation trench at least to a level substantially flush with an upper surface of the silicon active layer.
In one embodiment, the present invention relates to a silicon-on-insulator semiconductor device, including:
a silicon-on-insulator wafer having a silicon active layer, a dielectric insulation layer a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate;
wherein the at least one isolation trench includes a layer of a passivating insulator in a lower portion of the isolation trench.
In one embodiment of the device, the isolation trench above the passivating insulator includes a trench isolation material. In one embodiment of the device, the dielectric insulation layer, the passivating insulator and the trench isolation material comprise silicon dioxide. In one embodiment of the device, the passivating insulator is in contact with the dielectric insulation layer.
Thus, the present invention provides methods of STI applicable to SOI semiconductor devices which do not suffer from problems resulting from formation of a xe2x80x9cbird""s beakxe2x80x9d on the underside of the silicon active layer adjacent the isolation trench, while still allowing removal of the sharp corners from the silicon active islands.